PRACE Autumn-Summer School in Austria - Modern HPC Development for Scientists and Engineers, 27-30 September 2016


Deadline:

July 01, 2016

Event Date:

September 27, 2016 - September 30, 2016


Opportunity Cover Image - PRACE Autumn-Summer School in Austria - Modern HPC Development for Scientists and Engineers, 27-30 September 2016

Modern HPC Development for Scientists and Engineers

(Poster for the PRACE Autumn School 2016 can be found here.)

Following the tradition of the PRACE Spring School 2014, the PRACE Autumn School 2016 will take place on September 27-30 at the Castle of Hagenberg in Austria. The programme offers a unique opportunity to bring users, developers and industry together to learn more about the development of scalable applications on modern computer architectures (massively parallel systems as well as many-integrated-core architectures).

The four day program includes:

  • a 1-day presentation and interaction track bringing together researchers and attendees from industry and academia to discuss a variety of applications of HPC in Europe;
  • two 3-day workshop tracks with lecturers from industry and academia and hand-on sessions on
    • Parallel Programming with OpenMP and MPI
    • Intel Xeon Phi Programming
    • Parallel IO
    • PETSc: Portable, Extensible Toolkit for Scientific Computation
    • Tools for Performance Analysis
    • Advanced Parallel Programming

About the Autumn School Program in Austria

The program is free of charge (not including travel and accommodation). For the hands-on sessions, participants are expected to bring their own laptops.

Applications are open to researchers, academics and industrial researchers residing in PRACE member countries, and European Union Member States and Associated Countries. All lectures and training sessions will be in English.

This PRACE Seasonal School event is being hosted and coordinated jointly by the Research Institute for Symbolic Computation/Johannes Kepler University Linz (Austria), the RISC Software company, Hagenberg (Austria), and IT4Innovations/ VSB-Technical University of Ostrava (Czech Republic).

Registration Deadline: July 1, 2016.
Free of charge (not including travel and accommodation).
The number of places is limited.

Location

The Castle of Hagenberg is a medieval castle 20 km from Linz in the beautiful landscape of the Mühlviertel in Upper Austria. The village Hagenberg im Mühlkreis, where the castle is located, has about 2.650 inhabitants. Hagenberg is known for the JKU Softwarepark Hagenberg a major technology park focusing on IT, with research, education and business. Since the foundation of JKU Softwarepark Hagenberg in 1989, over 1.000 jobs and 1.500 study places have been created during a process of public growth. Hagenberg enjoys a high quality of life and an excellent standard of living. It is situated in the center of nature, yet within easy reach of the city of Linz. A great mix of shops, restaurants, bars as well as a number of physicians and a pharmacy supply the inhabitants of Hagenberg with the best possible infrastructure.

Accommodation & Transport

For the attendees at the PRACE Autumn School 2016 rooms have been reserved in Linz. A daily transfer service for attendees is arranged from Linz to the Castle of Hagenberg and back.

See this page for information on how to travel to Linz.

Scientific Programme

  • Parallel Programming
    This module focuses on two state-of-the-art programming models for HPC applications: OpenMP and MPI. For both programming models, basic as well as certain selected advanced topics (e.g. for MPI new features such as non-blocking or sparse neighbourhood collectives) are presented. For the MPI session, special attention is also put on best practices for achieving good program performance, based on the presenter’s experience from the support of recent PRACE Preparatory Access Type C projects.
  • Intel Xeon Phi Programming
    In this module, Intel’s Many Integrated Core (MIC) architecture is introduced. The session covers various programming models for Intel Xeon Phi coprocessors (like native mode vs. offload mode, OpenMP and MPI parallelisation etc.) as well as some selected optimisation techniques. Hands-on sessions are planned to take place on an Intel Xeon Phi based system at VSB.
  • Parallel-IO
    This module covers parallel IO concepts related with parallel file systems, IO techniques and performance analysis. Furthermore, it introduces the IO libraries MPI-IO, SIONlib and high level libraries HDF5 and NetCDF. The theoretical part will be complemented by practical exercises for each presented library.
  • PETSc Tutorial
    The Portable Extensible Toolkit for Scientific computing (PETSc) is a modular library for linear algebra, non-linear solvers, time integrators, optimization, and spatial discretization. Solver configuration and diagnostics are valuable skills for users, whether calling PETSc directly or via one of many higher level packages that access PETSc solvers. The tutorial will start with the fundamental linear algebra components then proceed to principles of preconditioning and Krylov solvers, convergence diagnostics, performance analysis, and the higher level solver interfaces. It will contain hands-on exercises to build the skills necessary to evaluate methods and design solvers for complex problems in science and engineering.
  • Tools for Performance Analysis
    This module gives an introduction to effective strategies for analysing performance and IO behaviour of HPC applications. The focus will lie on HPCToolkit for performance analysis as well as on Darshan, Vampir and TAU for IO Profiling and IO Tracing. Hands-on sessions shall lower the threshold for attendees to actually using these tools in the course of their every-day work.
  • Advanced Parallel Programming
    A first session deals with exploiting parallelism on Multi-Core CPUs considering memory hierarchies: The different levels of parallelism implemented in hardware are presented. For each level the implementation in hardware is illustrated. We analyse the relevance of each level from a programmer’s point of view and present memory hierarchies in more detail. We show the motivation for caching in hardware and what kind of problems arise from caching in a parallel context. Finally the roofline model is presented, which allows to estimate the performance of parallel algorithms. The second session presents an introduction to vectorization on Intel x86 CPUs from a programmer’s point of view. The different levels of the programmer's control over the vectorization are shown. Special focus lies in the auto vectorization support of the Intel C/C++ compiler.

For the links and more detailed information please click on "Further Official Information"  below.



Eligible Countries
Host Country
Study Levels
Publish Date
June 26, 2016
Link To Original




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