Correctness 2017: First International Workshop on Software Correctness for HPC Applications
Ensuring correctness in high-performance computing (HPC) applications is one of the fundamental challenges that the HPC community faces today. While significant advances in verification, testing, and debugging have been made to isolate software errors (or defects) in the context of non-HPC software, several factors make achieving correctness in HPC applications and systems much more challenging than in general systems software—growing heterogeneity (architectures with CPUs, GPUs, and special purpose accelerators), massive scale computations (very high degree of concurrency), use of combined parallel programing models (e.g., MPI+X), new scalable numerical algorithms (e.g., to leverage reduced precision in floating-point arithmetic), and aggressive compiler optimizations/transformations are some of the challenges that make correctness harder in HPC.
As the complexity of future architectures, algorithms, and applications in HPC increases, the ability to fully exploit exascale systems will be limited without correctness. With the continuous use of HPC software to advance scientific and technological capabilities, novel techniques and practical tools for software correctness in HPC are invaluable.
The goal of the Correctness Workshop is to bring together researchers and developers to present and discuss novel ideas to address the problem of correctness in HPC. The workshop will feature contributed papers and invited talks in this area.
Topics of interest include, but are not limited to:
- Formal methods and rigorous mathematical techniques for correctness in HPC applications/systems
- Frameworks to address the challenges of testing complex HPC applications (e.g., multiphysics applications)
- Approaches for the specification of numerical algorithms with the goal of correctness checking
- Error identification in the design and implementation of numerical algorithms using finite-precision floating point numbers
- Static and dynamic analysis to test and check correctness in the entire HPC software ecosystem
- Practical and scalable tools for model checking, verification, certification, or symbolic execution
- Analysis of error propagation and error handling in HPC libraries
- Techniques to control the effect of non-determinism when debugging and testing HPC software
- Scalable debugging solutions for large-scale HPC applications
- Predictive debugging and testing approaches to forecast the occurrence of errors in specific conditions
- Machine learning and anomaly detection approaches for bug detection and localization
- Metrics to measure the degree of correctness of HPC applications/systems
- Community-wide models to share past successes (e.g., bug report databases, reproducible test cases)
Submissions and Format
Authors are invited to submit manuscripts in English structured as technical or experience papers not exceeding 6 pages of content. The 6-page limit includes figures, tables and appendices, but does not include references, for which there is no page limit. Submissions must use the ACM format.
Submitted papers must represent original unpublished research that is not currently under review for any other venue. Papers not following these guidelines will be rejected without review. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered. At least one author of an accepted paper must register for and attend the workshop. Authors may contact the workshop organizers for more information.
The proceedings will be archived in both the ACM Digital Library and IEEE Xplore through SIGHPC.
- Paper submissions due: August 18, 2017
- Notification of acceptance: September 15, 2017
- Camera-ready papers due (firm): October 6, 2017
- Workshop: SC 2017, Sun, Nov 12 (at 9am-12:30pm), 2017
For more information please click "Further Official Information" below.
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